1. Field of the Invention
The invention relates to data processing systems and more particularly to a pipelined microprocessor and a method and apparatus therein for address calculation for different addressing modes.
2. Description of the Related Art
Users of modern computers are demanding greater speed in the form of increased throughput (number of completed tasks per unit of time) and increased speed (reduced time it takes to complete a task). The Reduced Instruction Set Computer (RISC) architecture is one approach system designers have taken to achieve this. Generally a RISC machine can issue and execute an instruction per clock cycle. In a RISC machine only a very few instructions can access memory, so most instructions use on-chip registers.
In a process or with a 4Kbyte page size, the upper 20 bits of an address are needed by the virtual-to-physical address translator. Experience has shown that the most common offset calculations involve the lower 12 bits of the address and require a page crossing in less than 5 percent of all cases.
It is therefore an object of the invention to provide an addressing mode speedup method and means which improves the performance of some very frequently used addressing modes.
The invention has the advantages that it improves the "base-plus-displacement/offset" and the "scaled-index-plus-displacement" addressing modes by one clock most of the time.
The invention has the further advantage that address calculations are performed in one clock cycle for frequently used addressing modes.